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general description the MAX11156 18-bit, 500ksps, sar adc offers excel - lent ac and dc performance with true bipolar input range, small size, and internal reference. the MAX11156 mea - sures a 5v (10v p-p ) input range while operating from a single 5v supply. a patented charge-pump architecture allows direct sampling of high- impedance sources. the MAX11156 integrates an optional 6ppm/c reference with internal buffer, saving the cost and space of an external reference. the MAX11156 produces 94.6db snr and -105db thd (typ). the MAX11156 guarantees 18-bit no-missing codes. the MAX11156 communicates using an spi-compatible serial interface at 2.5v, 3v, 3.3v, or 5v logic. the serial interface can be used to daisy-chain multiple adcs in parallel for multichannel applications and provides a busy indicator option for simplified system synchronization and timing. the MAX11156 is offered in a 12-pin, 3mm x 3mm, tdfn package and is specified over the -40c to +85c tem - perature range. applications data acquisition systems industrial control systems/process control medical instrumentation automatic test equipment features high dc and ac accuracy 18-bit resolution with no missing codes snr: 94.6db thd: -105db at 10khz 2.5 lsb inl (typ) 0.4 lsb dnl (typ) internal reference and reference buffer save cost and board space 6ppm/c (typ) tiny 12-pin 3mm x 3mm tdfn package bipolar 5v analog input range saves external signal conditioning single-supply adc with low power 5v analog supply 2.3v to 5v digital supply 26.5mw at 500ksps shutdown mode 500ksps throughput rate no pipeline delay/latency flexible industry-standard serial interface saves i/o pins spi/qspi?/microwire ? /dsp-compatible 19-6622; rev 0; 3/13 typical operating circuit selector guide and ordering information appear at end of data sheet. qspi is a trademark of motorola, inc. microwire is a registered trademark of national semiconductor corporation. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX11156.related . evaluation kit available max9632 agnds 18-b it ad c ref buf configuration registe r internal referenc e ain+ ain- ref cnvst gnd refio dout din sclk 1 f1 f v dd (5v) ovdd (2.3v to 5v) interfac e and contro l host controller 5v 50 500pf 10f MAX11156 0.1f MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn
maxim integrated 2 v dd to gnd ............................................................ -0.3v to +6v ovdd to gnd ....... -0.3v to the lower of (v dd + 0.3v) and +6v ain+ to gnd ........................................................................ q 7v ain-, ref, refio, agnds to gnd ............... -0.3v to the lower of (v dd + 0.3v) and +6v sclk, din, dout, cnvst to gnd ............... -0.3v to the lower of (v dd + 0.3v) and +6v maximum current into any pin ........................................... 50ma continuous power dissipation (t a = +70 n c) tdfn (derate 18.2mw/ n c above +70 n c) .................. 1349mw operating temperature range ........................... -40 n c to +85 n c junction temperature ...................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................. +300 n c soldering temperature (reflow) ....................................... +260 n c absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v dd = 4.75v to 5.25v, v ovdd = 2.3v to 5.25v, f sample = 500khz, v ref = 4.096v, reference mode 3; t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . tdfn junction-to-ambient thermal resistance ( q ja ) ........ 59.3c/w junction-to-case thermal resistance ( q jc ) ............ 22.5c/w (note 1) package thermal characteristics parameter symbol conditions min typ max units analog input (note 3) input voltage range ain+ to ain-, k = 5.0/4.096 -k x v ref +k x v ref v absolute input voltage range ain+ to gnd -(v dd + 0.1) +(v dd + 0.1) v ain- to gnd -0.1 +0.1 input leakage current acquisition phase -10 +0.001 +10 a input capacitance 15 pf input-clamp protection current both inputs -20 +20 ma dc accuracy (note 4) resolution n 18 bits no missing codes 18 bits offset error -1.5 0.1 +1.5 mv -40 2.6 +40 lsb offset temperature coeffcient 2.4 v/c gain error -40 8 +40 lsb gain error temperature coeffcient 1 ppm/c integral nonlinearity t a = t min to t max -8 2.5 +8 lsb t a = +25c to +85c -6 2.5 +6 differential nonlinearity dnl -0.9 0.5 +0.9 lsb positive full-scale error -55 +55 lsb negative full-scale error -45 +45 lsb MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 3 electrical characteristics (continued) (v dd = 4.75v to 5.25v, v ovdd = 2.3v to 5.25v, f sample = 500khz, v ref = 4.096v, reference mode 3; t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units analog input cmr cmr -77 db power-supply rejection (note 5) psr 8.0 lsb transition noise 1.7 lsb rms reference (note 7) ref output initial accuracy v ref reference mode 0 4.092 4.096 4.100 v ref output temperature coeffcient tc ref reference mode 0 -17 9 +17 ppm/c refio output initial accuracy v refio reference modes 0 and 2 4.092 4.096 4.100 v refio output temperature coeffcient tcrefio reference modes 0 and 2 -15 6 +15 ppm/c refio output impedance reference modes 0 and 2 10 k refio input voltage range reference mode 1 3 4.096 4.25 v reference buffer initial offset reference mode 1 -500 +500 v reference buffer temperature coeffcient reference mode 1 -10 6 +10 v/c external compensation capacitor c ext required for reference modes 0 and 1, recommended for reference modes 2 and 3 10 f ref voltage input range v ref reference modes 2 and 3 2.5 4.25 v ref input capacitance reference modes 2 and 3 20 pf ref load current 130 a ac accuracy (note 6) signal-to-noise ratio (note 7) snr f in = 10khz v ref = 4.096v, reference mode 3 93 94.6 db v ref = 4.096v, reference mode 1 93.7 v ref = 2.5v, reference mode 3 90.6 internal reference, reference mode 0 93.6 signal-to-noise plus distortion (note 7) sinad f in = 10khz v ref = 4.096v, reference mode 3 91.5 94.2 db v ref = 4.096v, reference mode 1 93.0 v ref = 2.5v, reference mode 3 90.2 internal reference, reference mode 0 92.8 MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 4 electrical characteristics (continued) (v dd = 4.75v to 5.25v, v ovdd = 2.3v to 5.25v, f sample = 500khz, v ref = 4.096v, reference mode 3; t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units spurious-free dynamic range sfdr 96 105 db total harmonic distortion thd -105 -96 db intermodulation distortion (note 8) imd -115 dbfs sampling dynamics throughput sample rate 0.01 500 ksps transient response full-scale step 400 ns full-power bandwidth -3db point 6 mhz -0.1db point > 0.2 aperture delay 2.5 ns aperture jitter 50 ps rms power supplies analog supply voltage v dd 4.75 5.25 v interface supply voltage v ovdd 2.3 5.25 v analog supply current i vdd internal reference mode 5.0 6.0 6.5 ma external reference mode 3.0 3.6 4.0 v dd shutdown current 6.3 10 a interface supply current (note 9) v ovdd = 2.3v 1.7 2.0 ma v ovdd = 5.25v 4.4 5.0 ovdd shutdown current 0.9 10 a power dissipation v dd = 5v, v ovdd = 3.3v, reference mode = 2 and 3 26.5 mw v dd = 5v, v ovdd = 3.3v, reference mode = 0 and 1 38.5 digital inputs (din, sclk, cnvst) input voltage high v ih 0.7 x v ovdd v input voltage low v il 0.3 x v ovdd v input hysteresis v hys 0.05 x v ovdd v input capacitance c in 10 pf input current i in v in = 0v or v ovdd -10 +10 a digital output (dout) output voltage high v oh i source = 2ma v ovdd - 0.4 v MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 5 electrical characteristics (continued) (v dd = 4.75v to 5.25v, v ovdd = 2.3v to 5.25v, f sample = 500khz, v ref = 4.096v, reference mode 3; t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units output voltage low v ol i sink = 2ma 0.4 v three-state leakage current -10 +10 a three-state output capacitance 15 pf timing (note 9) time between conversions t cyc 2 100000 s conversion time t conv cnvst rising to data available 1.35 1.5 s acquisition time t acq t acq = t cyc - t conv 0.5 s cnvst pulse width t cnvpw cs mode 5 ns sclk period ( cs mode) t sclk v ovdd > 4.5v 14 ns v ovdd > 2.7v 20 v ovdd > 2.3v 26 sclk period ( daisy-chain mode) t sclk v ovdd > 4.5v 16 ns v ovdd > 2.7v 24 v ovdd > 2.3v 30 sclk low time t sclkl 5 ns sclk high time t sclkh 5 ns sclk falling edge to data valid delay t ddo v ovdd > 4.5v 12 ns v ovdd > 2.7v 18 v ovdd > 2.3v 23 cnvst low to dout d15 msb valid ( cs mode) t en v ovdd > 2.7v 14 ns v ovdd < 2.7v 17 cnvst high or last sclk falling edge to dout high impedance t dis cs mode 20 ns din valid setup time from sclk falling edge t sdinsck v ovdd > 4.5v 3 ns v ovdd > 2.7v 5 v ovdd > 2.3v 6 din valid hold time from sclk falling edge t hdinsck 0 ns sclk valid setup time to cnvst falling edge t ssckcnf 3 ns sclk valid hold time to cnvst falling edge t hsckcnf 6 ns MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 6 typical operating characteristics ( v dd = 5v, v ovdd = 3.3v, f sample = 500khz, v ref = 4.096v, reference mode 3, t a = +25 n c, unless otherwise noted .) note 2: maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of +25c and +85c. limits below +25c are guaranteed by design and device characterization. typical values are not guaranteed. note 3: see the analog inputs and overvoltage input clamps sections. note 4: see the definitions section. note 5: defined as the change in positive full-scale code transition caused by a q 5% variation in the v dd supply voltage. note 6: 10khz sine wave input, -0.1db below full scale. note 7: see table 4 for definition of the reference modes. note 8: f in1 = 9.4khz, f in2 = 10.7khz, each tone at -6.1db below full scale. note 9: c load = 65pf on dout. electrical characteristics (continued) (v dd = 4.75v to 5.25v, v ovdd = 2.3v to 5.25v, f sample = 500khz, v ref = 4.096v, reference mode 3; t a = t min to t max , unless otherwise noted. typical values are at t a = +25 n c.) (note 2) offset and gain error vs. temperature MAX11156 toc01 temperature (c) error (lsb) 60 35 -15 10 -15 -10 -5 0 10 5 15 20 -20 -40 85 offset error (lsb) gain error (lsb) average of 128 devices offset and gain error vs. supply voltage MAX11156 toc02 v dd (v) error (lsb) 5.15 5.05 4.85 4.95 -15 -10 -5 0 10 5 15 20 -20 4.75 5.25 offset error (lsb) gain error (lsb) average of 128 devices output noise histogram with input connected to gnd MAX11156 toc03 output code (decimal) number of occurences 131071 131067 131073 131077 131075 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 131079 131069 131065 single device integral nonlinearity vs. code MAX11156 toc04 output code (decimal) inl (lsb) 229376 196608 32768 65536 98304 131072 163840 -3 -2 -1 0 1 2 3 4 -4 0 262144 single device inl vs. temperature MAX11156 toc05 temperature (c) inl (lsb) 60 35 -15 10 -6 -4 -2 0 4 2 6 8 -8 -40 85 max inl min inl average of 128 devices inl vs. v dd supply voltage MAX11156 toc06 v dd (v) inl (lsb) 5.15 5.05 4.85 4.95 -6 -4 -2 0 4 2 6 8 -8 4.75 5.25 max inl min inl average of 128 devices MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 7 typical operating characteristics (continued) ( v dd = 5v, v ovdd = 3.3v, f sample = 500khz, v ref = 4.096v, reference mode 3, t a = +25 n c, unless otherwise noted .) differential nonlinearity vs. code MAX11156 toc07 dnl (lsb) -0.5 0 0.5 1.0 -1.0 output code (decimal) 229376 196608 32768 65536 98304 131072 163840 0 262144 single device internal reference voltage (ref pin) vs. temperature MAX11156 toc10 4.091 4.092 4.093 4.094 4.095 4.096 4.097 4.098 4.099 4.100 4.101 4.102 4.090 temperature (c) 60 35 10 -15 -40 85 v ref (v) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 fft plot MAX11156 toc13 frequency (khz) magnitude (db) 200 150 100 50 -120 -100 -80 -60 -40 -20 0 -140 0 250 f sample = 500ksps n sample = 4096 f in = 11597hz v in = -0.1dbfs ref mode = 0 v ref = 4.096v single device snr = 93.8db sinad = 93.8db sfdr = 105.4db thd = -103.4db dnl vs. temperature MAX11156 toc08 temperature (c) dnl (lsb) 60 35 10 -15 -0.6 -0.2 0.2 0.6 1.0 -1.0 -40 85 max dnl min dnl average of 128 devices initial error voltage on ref pin MAX11156 toc11 ref pin voltage (v) number of occurences 10 20 30 40 50 0 4.095 4.096 4.097 4.098 4.099 4.094 4.093 303 devices mean = 4096.0mv dnl vs. v dd supply voltage MAX11156 toc09 v dd (v) dnl (lsb) 5.15 5.05 4.95 4.85 -0.6 -0.2 0.2 0.6 1.0 -1.0 4.75 5.25 max dnl min dnl average of 128 devices ref pin thermal drift slope MAX11156 toc12 thermal drift (ppm/c) number of occurences 10 8 6 4 2 0 -4 -8 -2 -6 -10 -12 -14 10 20 30 40 50 60 70 0 -16 12 303 devices mean = -7.3ppm/c stdev = 1.9ppm/c 303 devices mean = 2.1ppm/c stdev = 1.9ppm/c +25c to -40c +25c to -85c fft plot MAX11156 toc14 frequency (khz) magnitude (db) 200 150 50 100 -120 -100 -80 -60 -20 0 -40 -140 0 250 f sample = 500ksps n sample = 4096 f in = 10132hz v in = -0.1dbfs ref mode = 3 v ref = 4.096v single device snr = 94.6db sinad = 94.2db sfdr = 105.6db thd = -104.5db two tones imd MAX11156 toc15 frequency (khz) magnitude (db) 13 11 7 9 -120 -100 -80 -60 -20 0 -40 -140 5 15 f sample = 500ksps n sample = 16384 f in1 = 9368.9hz v in1 = -6.1dbfs f in2 = 10651hz v in2 = -6.1dbfs ref mode = 3 v ref = 4.096v single device imd = -116.9dbfs www.maximintegrated.com MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn
maxim integrated 8 typical operating characteristics (continued) ( v dd = 5v, v ovdd = 3.3v, f sample = 500khz, v ref = 4.096v, reference mode 3, t a = +25 n c, unless otherwise noted .) thd vs. temperature MAX11156 toc21 temperature (c) thd (db) 60 35 10 -15 -106 -104 -102 -100 -98 -108 -40 85 f sample = 500ksps f in = 10khz v in = -0.1dbfs ref mode = 3 v ref = 4.096v average of 128 devices temperature (c) snr and sinad (db) 60 35 10 -15 93.5 94.0 94.5 95.0 95.5 96.0 93.0 -40 85 snr and sinad vs. temperature MAX11156 toc19 snr sinad f sample = 500ksps f in = 10khz v in = -0.1dbfs ref mode = 3 v ref = 4.096v average of 128 devices frequency (khz) sfdr and -thd (db) 10 1 0.1 100 sfdr and -thd vs. input frequency MAX11156 toc18 90 95 100 105 110 115 85 -thd sfdr f sample = 500ksps f in = 10khz v in = -0.1dbfs ref mode = 3 v ref = 4.096v average of 128 devices frequency (khz) sinad (db) 10 1 0.10 100 sinad vs. frequency MAX11156 toc16 86 88 90 92 94 96 84 f sample = 500ksps f in = 10khz v in = -0.1dbfs ref mode = 3 v ref = 4.096v average of 128 devices psrr vs. input frequency MAX11156 toc24 frequency (khz) psrr (db) 100 10 1 -80 -75 -70 -65 -60 -55 -85 0.1 1000 f sample = 500ksps ref mode = 3 v ref = 4.096v v vdd = 5.0 56mv v ovdd = 3.3v single device cmrr vs. input frequency MAX11156 toc23 frequency (khz) cmrr (db) 10.0 1.0 -80 -70 -60 -50 -40 -90 0.1 100.0 f sample = 500ksps ref mode = 3 v ref = 4.096v v ain+ = v ain- = 100mv p-p single device snr and sinad vs. v dd supply voltage MAX11156 toc20 v dd (v) snr and sinad (db) 5.15 5.05 4.95 4.85 93.5 94.0 94.5 95.0 95.5 93.0 4.75 5.25 snr sinad f sample = 500ksps f in = 10khz v in = -0.1dbfs ref mode = 3 vref = 4.096v average of 128 devices v dd (v) thd (db) 5.15 5.05 4.95 4.85 -110 -108 -106 -104 -102 -100 -112 4.75 5.25 thd vs. v dd supply voltage MAX11156 toc22 f sample = 500ksps f in = 10khz v in = -0.1dbfs ref mode = 3 v ref = 4.096v average of 128 devices enob vs. input signal frequency MAX11156 toc17 frequency (khz) enob (bits) 10 1 14.0 14.2 14.4 14.6 14.8 15.0 15.2 15.4 15.6 13.8 0.10 100 f sample = 500ksps f in = 10khz v in = -0.1dbfs ref mode = 3 v ref = 4.096v average of 128 devices www.maximintegrated.com MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn
maxim integrated 9 typical operating characteristics (continued) ( v dd = 5v, v ovdd = 3.3v, f sample = 500khz, v ref = 4.096v, reference mode 3, t a = +25 n c, unless otherwise noted .) v dd (v) i vdd (ma) 5.15 5.05 4.95 4.85 3 4 5 6 7 8 2 4.75 5.25 v dd supply current vs. v dd supply voltage MAX11156 toc26 ref mode 0 and 1 ref mode 2 and 3 average of 128 devices analog and digital shutdown current vs. temperature MAX11156 toc29 temperature (c) shutdown current (a) 60 35 10 -15 2 4 6 8 10 0 -40 85 ivdd iovdd average of 128 devices ovdd supply current vs. temperature MAX11156 toc27 temperature (c) i ovdd (ma) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 -40 85 at 500ksps at 10ksps c dout = 65pf average of 128 devices ovdd supply current vs. ovdd supply voltage MAX11156 toc28 v ovdd (v) i ovdd (ma) 4.75 4.25 3.75 3.25 2.75 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 2.25 5.25 at 500ksps at 10ksps c dout = 65pf average of 128 devices v dd and ovdd shutdown current vs. supply voltage MAX11156 toc30 v dd or v ovdd (v) shutdown current (a) 4.75 4.25 2.75 3.25 3.75 1 2 3 4 5 6 7 8 0 2.25 5.25 ivdd iovdd temperature (c) i vdd (ma) 60 35 10 -15 3 4 5 6 7 8 2 -40 85 v dd supply current vs. temperature MAX11156 toc25 ref mode 0 and 1 ref mode 2 and 3 average of 128 devices www.maximintegrated.com MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn
maxim integrated 10 pin confguration pin description pin name i/o function 1 refio i/o external reference input/internal reference output. place a 0.1f capacitor from refio to agnds. 2 ref i/o external reference input/reference buffer decoupling. bypass to agnds in close proximity with a x5r or x7r 10f 16v chip. see the layout , grounding , and bypassing section. 3 v dd i analog power supply. bypass to gnd with a 0.1f capacitor for each device and one 10f per pcb. 4 ain+ i positive analog input 5 ain- i negative analog input. connect ain- to the analog ground plane or to a remote-sense ground. 6 gnd i power-supply ground 7 cnvst i convert start input. the rising edge of cnvst initiates conversions. the falling edge of cnvst with sclk high enables the serial interface. 8 dout o serial data output. dout will change stated on the falling edge of sclk. 9 sclk i serial clock input. clocks data out of the serial interface when the device is selected. 10 din i serial data input. din data is latched into the serial interface on the rising edge of sclk. 11 ovdd i digital power supply. bypass to gnd with a 0.1f capacitor for each device and one 10f per pcb. 12 agnds i analog ground sense. zero current reference for the on-board dac and reference source. reference for refio and ref. ep exposed pad. ep is connected internally to gnd. connect to pcb gnd. 1 3 4 12 10 9 8 agnds din sclk dout max11 156 2 11 ovdd 5 6 + 7 cnvst refio v dd ain+ ain- ref gnd ep tdfn top view MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 11 functional diagram detailed description the MAX11156 is an 18-bit single-channel, pseudo-differ - ential adc with a maximum throughput rates of 500ksps. this adc includes a precision internal reference that allows for measuring a bipolar input voltage range of q 5v. an external reference can also be applied for input ranges between q 3.05v and q 5.19v. both inputs (ain+ and ain-) are sampled with a pseudo-differential on-chip track-and- hold exhibiting no pipeline delay or latency, making these adcs ideal for multiplexed applications. the MAX11156 measures a true bipolar voltage of q 5v (10v p-p ) and the inputs are protected for up to q 20ma of overrange current. this adc is powered from a 4.75v to 5.25v analog supply (v dd ) and a separate 2.3v to 5.25v digital supply (ovdd). the MAX11156 requires 500ns to acquire the input sample on an internal track-and-hold and then convert the sampled signal to 18 bits of accuracy using an internally clocked converter. analog inputs the MAX11156 adc consists of a true sampling pseudo- differential input stage with high-impedance, capacitive inputs. the internal t/h circuitry feature a small-signal bandwidth of about 6mhz to provide 18-bit accurate sampling in 500ns. this allows for accurate sampling of a number of scanned channels through an external mul - tiplexer. the MAX11156 can thus convert input signals on ain+ in the range of -(k o v ref + ain-) to +(k o v ref + ain-) where k = 5.000/4.096. ain+ should also be limited to (v dd + 0.1v) for accurate conversions. ain- has an input range of -0.1v to +0.1v and should be connected to the ground reference of the input signal source. the MAX11156 performs a true differential sample on inputs between ain+ and ain- with good common-mode rejec - tion (see the typical operating circuit ). this allows for improved sampling of remote transducer inputs. many traditional adcs with single supplies that mea - sure bipolar input signals use resistive divider networks directly on the analog inputs. these networks increase the complexity of the input signal conditioning. however, the MAX11156 includes a patented input switch architec - ture which allows direct sampling onto the input sample and hold capacitor without the use of scaling resistor net - works. this results in zero source loading errors when the sample and hold is allowed to fully settle. this architec - ture requires a minimum sample rate of 10hz to maintain accurate conversions over the designed temperature and supply ranges. 18-b it ad c configuration registe r ref buf internal referenc e ain+ ain- agnds sw1 10k refio cnvst dout ref gnd ovdd v dd sclk din interfac e and contro l MAX11156 sw2 configuration register reference mode reference switch state b5 0 0 1 1 b4 0 1 0 1 sw2 closed closed open open sw1 closed open closed open 0 1 2 3 MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 12 overvoltage input clamps the MAX11156 includes an input clamping circuit that activates when the input voltage at ain+ is above (v dd + 300mv) or below -(v dd + 300mv). the clamp circuit remains high impedance while the input signal is within the range of q (v dd + 100mv) and draws little to no cur - rent. however, when the input signal exceeds this range the clamps begin to turn on. consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed the range of q (v dd + 100mv). to make use of the input clamps, connect a resistor (r s ) between the ain+ input and the voltage source to limit the voltage at the analog input and to ensure the fault current into the devices does not exceed q 20ma. note that the voltage at the ain+ input pin limits to approximately 7v during a fault condition so the following equation can be used to calculate the value of r s : max fault s v 7v r 20ma ? = where v fault max is the maximum voltage that the source produces during a fault condition. figure 1 and figure 2 illustrate the clamp circuit volt - age current characteristics for a source impedance r s = 1280 i . while the input voltage is within the q (v dd + 300mv) range, no current flows in the input clamps. once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin. internal/external reference 5(),2rjxudwlr the MAX11156 includes a standard spi interface that selects internal or external reference modes of opera - tion through an input configuration register (see the input configuration interface section). the MAX11156 features an internal bandgap reference circuit (v refio = 4.096v) that is buffered with an internal reference buffer that drives the ref pin. the MAX11156 configure regis - ter allows four combinations of reference configuration. these reference mode are: reference mode 00: adc reference is provided by the internal bandgap feed out the refio pin, noise filtered with an external capacitor on the refio pin, then buff - ered by the internal reference buffer and decoupled with an external capacitor on the ref pin. in this mode the adc requires no external reference source. reference mode 01: adc reference is provided exter - nally and feeds into the refio pin, buffered with the internal reference buffer and decoupled with an external capacitor on the ref pin. this mode is typically used when a common reference source is needed for more than one MAX11156. reference mode 10: the internal bandgap is used as a reference source output and feed out to the refio pin. however, the internal reference buffer is in a shutdown state and the ref pin is high impedance. this state would typically be used to provide a common reference source to a set of external reference buffers for several MAX11156. figure 1. input clamp characteristics figure 2. input clamp characteristics (zoom in) MAX11156 input clam p characteristics signal voltage at source and ain+ input (v ) i clamp (ma) 30 20 0 10 -20 -10 -30 -20 -15 -10 -5 0 5 10 15 20 25 -25 -40 40 r s = 1280i v dd = 5.0v ain+ pin input source MAX11156 input clam p characteristics signal voltage at source and ain+ input (v ) i clamp (ma) 6 4 0 2 -4 -2 -6 -20 -15 -10 -5 0 5 10 15 20 25 -25 -8 8 r s = 1280i v dd = 5.0v ain+ pin input source MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 13 reference mode 11: the internal bandgap reference source as well as the internal reference buffer are both in a shutdown state. the ref pin is in a high-impedance state. this mode would typically be used when an exter - nal reference source and external reference buffer is used to drive all MAX11156 parts in a system. regardless of the reference mode used, the MAX11156 requires a low-impedance reference source on the ref pin to support 18-bit accuracy. when using the internal reference buffer, externally bypass the reference buffer output using at least a 10 f f, low-inductance, low-esr capacitor placed as close as possible to the ref pin, thus minimizing additional pcb inductance. when using the internal bandgap reference source, bypass the refio pin with a 0.1 f f capacitor to ground. if providing an external reference and using the internal reference buffer, drive the refio pin directly with an external reference source in the range of 3.0v to 4.25v. finally, if disabling the MAX11156 internal bandgap reference source and inter - nal reference buffer, drive the ref pin with a reference voltage in the range of 2.5v to 4.25v and place at least a 10 f f, low-inductance, low-esr capacitor placed as close as possible to the ref pin . when using the MAX11156 in external reference mode, it is recommended that an external reference buffer be used. for bypass capacitors on the ref pin, x7r or x5r ceramic capacitors in a 1210 case size or smaller have been found to provide adequate bypass performance. y5u or z5u ceramic capacitors are not recommended due to their high voltage and temperature coefficients. maxim offers a wide range of precision references ideal for 18-bit accuracy. table 1 lists some of the options rec - ommended. input amplifer the conversion results are accurate when the adc acquires the input signal for an interval longer than the input signal's settling time. the adc input sampling capacitor charges during the acquisition period. during this acquisition period, the settling of the sampled voltage is affected by the source resistance and the input sam - pling capacitance. sampling error can be estimated by modeling the time constant of the total input capacitance and the driving source impedance. although the MAX11156 is easy to drive, an amplifier buf - fer is recommended if the source impedance is such that when driving a switch capacitor of ~20pf a significant settling error in the desired sampling period will occur. if this is the case, it is recommended that a configuration shown in the typical operating circuit is used where at least a 500pf capacitor is attached to the ain+ pin. this capacitance reduces the size of the transient at the start of the acquisition period, which in some buffers will cause an input signal dependent offsets. regardless of whether an external buffer amp is used or not, the time constant, r source c load , of the input should not exceed t acq /13, where r source is the total signal source impedance, c load is the total capacitance at the adc input (external and internal) and t acq is the acquisition period. thus to obtain accurate sampling in a 500ns acquisition time a source impedance of less than 1042 should be used if driving the adc directly. when driving the adc from a buffer, it is recommended a series resistance (5 to 50 typical) between the amplifier and the external input capacitance as shown in the typical operating circuit . we report some amplifier features to select the adc driver. 1) fast settling time: for multichannel multiplexed appli - cations the driving operational amplifier must be able to settle to 18-bit resolution when a full-scale step is applied during the minimum acquisition time. 2) low noise: it is important to ensure that the driver amplifier has a low average noise density appropriate for the desired bandwidth of the application. when the MAX11156 is used with its full bandwidth of 6mhz, it table 1. MAX11156 external reference recommendations part v out (v) temperature coefficient (max) initial accuracy (%) noise (0.1hz to 10hz) (v p-p ) package max6126 2.5, 3, 4.096, 5.0 3 (a), 5 (b) 0.06 1.35 max-8 so-8 max6325 2.5 1 0.04 1.5 so-8 max6341 4.096 1 0.02 2.4 so-8 MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 14 is preferable to use an amplifier that will produce an output noise spectral density of less than 6nv/ hz , to ensure the overall snr is not degraded significantly. it is recommended to insert an external rc filter at the MAX11156 ain+ input to attenuate out-of-band input noise and preserve the adc's snr. the effec - tive rms noise at the MAX11156 ain+ input is 65 f v, thus additional noise from a buffer circuit should be significantly lower in order to achieve the maximum snr performance. 3) thd performance: the input buffer amplifier used should have a comparable thd performance with that of the MAX11156 to ensure the thd of the digitized signal is not degraded. table 2 summarizes the operational amplifiers that are compatible with the MAX11156. the max9632 has suf - ficient bandwidth, low enough noise and distortion to sup - port the full performance of the MAX11156. the max9633 is a dual amp and can support buffering for true pseudo- differential sampling. transfer function the ideal transfer characteristic for the MAX11156 is shown in figure 3 . the precise location of various points on the transfer function are given in table 3 . table 2. list of recommended adc driver op amps for MAX11156 figure 3. bipolar transfer function table 3. transfer function example amplifier input-noise density (nv/ hz ) small-signal bandwidth (mhz) slew rate (v/s) thd (db) i cc (ma) comments max9632 1 55 30 -128 3.9 single amp, low noise, low thd max9633 3 27 18 -128 3.5 dual amp, low noise, low thd code transition bipolar input (v) digital output code (hex) +fs - 1.5 lsb +4.999943 3fffe - 3ffff midscale + 0.5 lsb +0.000019 20000 - 20001 midscale 0 20000 midscale - 0.5 lsb -0.000019 1ffff - 20000 -fs + 0.5 lsb -4.999981 00000 - 00001 transition 1fffe 00001 00000 20000 1ffff 20001 -fs 0 +fs 3ffff 3fffe outputcode (hex) input voltage (lsb) -fs + 0.5 lsb +fs - 1.5 lsb +fs - 1lsb +fs = 5 x v ref 4.096 lsb = +fs - (-fs) 262144 -fs = -5 x v ref 4.096 MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 15 input confguration interface an spi interface clocked at up to 50mhz controls the MAX11156. input configuration data is clocked into the configuration register on the falling edge of sclk through the din pin. the data on din is used to program the adc configuration register. the construct of this register is illustrated in table 4 . the configuration register defines the output interface mode, the reference mode, and the power-down state of the MAX11156. confguring in cs mode figure 4 details the timing for loading the input configura - tion register when the MAX11156 is connected in cs mode (see figure 6 and figure 8 for hardware connections). the load process is enabled on the falling edge of cnvst when sclk is held high. the configuration data is clocked into the configuration register through din on the next 8 sclk falling edges. pull cnvst high to complete the input configuration register load process. din should idle high outside an input configuration register read. table 4. adc configuration register figure 4. input configuration timing in cs mode bit name bit default state logic state function mode 7:6 00 00 cs mode, no-busy indicator 01 cs mode, with busy indicator 10 daisy-chain mode, no-busy indicator 11 daisy-chain mode, with busy indicator ref 5:4 00 00 reference mode 0. internal reference and reference buffer are both powered on. 01 reference mode 1. internal reference is turned off, but internal reference buffer powered on. apply the external reference voltage at refio. 10 reference mode 2. internal reference is powered on, but the internal reference buffer is powered off. this mode allows for internal reference to be used with an external reference buffer. 11 reference mode 3. internal reference and reference buffer are both powered off. apply an external reference voltage at ref. shdn 3 0 0 normal mode. all circuitry is fully powered up at all times. 1 static shutdown. all circuitry is powered down. reserved 2:0 0 0 reserved, set to 0 01234 56 7 t hsckcnf t ssckcnf cnvst sclk din t hdinsck t sdinsck b6 b5 b4 b3 b2 b1 b0 b7 MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 16 confguring in daisy-chain mode figure 5 details the configuration register load process when the MAX11156 is connected in a daisy-chain con - figuration (see figure 12 and figure 14 for hardware con - nections). the load process is enabled on the falling edge of cnvst when sclk is held high. in daisy-chain mode, the input configuration registers are chained together through dout to din. device as dout will drive device bs din. the input configuration register is an 8-bit, first- in first-out shift register. the configuration data is clocked in n times through 8 o n falling sclk edges. after the MAX11156 adc in the chain is loaded with the configura - tion byte, pull cnvst high to complete the configuration register loading process. figure 5 illustrates a configura - tion sequence for loading two devices in a chain. data loaded into the configuration register alters the state of the MAX11156 on the next conversion cycle after the regis - ter is loaded. however, powering up the internal reference buffer or stabilizing the refio pin voltage will take several milliseconds to settle to 18-bit accuracy. shutdown mode the shdn bit in the configuration register forces the MAX11156 into and out of shutdown. set shdn to 0 for normal operation. set shdn to 1 to shut down all internal circuitry and reset all registers to their default state. output interface the MAX11156 can be programmed into one of four out - put modes; cs modes with and without busy indicator and daisy-chain modes with and without busy indicator. when operating without busy indication, the user must exter - nally timeout the maximum adc conversion time before commencing readback. when operating in one of the two busy indication modes, the user can connect the dout output of the MAX11156 to an interrupt input on the digital host and use this interrupt to trigger the output data read. regardless of the output interface mode used, digital activity should be limited to the first half of the conversion phase. having sclk or din transitions near the sampling instance can also corrupt the input sample accuracy. therefore, keep the digital inputs quiet for approximately 25ns before and 10ns after the rising edge of cnvst. these times are denoted as t sq and t hq in all subse - quent timing diagrams. in all interface modes, the data on dout is valid on both sclk edges. however, the input setup time into the receiving digital host will be maximized when data is clocked into that digital host on the falling sclk edge. doing so will allow for higher data transfer rates between the MAX11156 and the digital host and consequently higher converter throughput. in all interface modes, it is recommended that the sclk be idled low to avoid triggering an input configuration write on the falling edge of cnvst. if at anytime the device detects a high sclk state on a falling edge of cnvst, it will enter the input configuration write mode and will write the state of din on the next 8 falling sclk edges to the input configuration register. in all interface modes, all data bits from a previous con - version must be read before reading bits from a new conversion. when reading out conversion data, if too few sclk falling edges are provided and all data bits are not read out, only the remaining unread data bits will be outputted during the next readout cycle. in such an event, the output data in every other readout cycle will appear to have been truncated as only the leftover bits from the previous readout cycle are outputted. figure 5. input configuration timing in daisy-chain mode b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 t hsckcnf t sdinsck t hdinsck da ta loaded to pa rt b shifted through pa rt a da ta loaded to pa rt a t ssckcnf cnvst 01 23456701 234567 sclk din MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 17 this is an indication to the user that there are insufficient sclk falling edges in a given readout cycle. table 5 provides a guide to aid in the selection of the appropriate output interface mode for a given application. cs no-busy indicator mode the cs no-busy indicator mode is ideally suited for maximum throughput when a single MAX11156 is con - nected to a spi-compatible digital host. the connection diagram is shown in figure 6 , and the corresponding timing is provided in figure 7 . a rising edge on cnvst completes the acquisition, initi - ates the conversion, and forces dout to high impedance. the conversion continues to completion irrespective of the state of cnvst allowing cnvst to be used as a select line for other devices on the board. if cnvst is brought low during a conversion and held low throughout the maximum conversion time, the msb will be output at the end of the conversion. when the conversion is complete, the MAX11156 enters the acquisition phase. drive cnvst low to out - put the msb onto dout. the remaining data bits are then clocked by subsequent sclk falling edges. dout returns to high impedance after the 18th sclk falling edge, or when cnvst goes high. table 5. adc output interface mode selector guide figure 6. cs no-busy indicator mode connection diagram mode typical application and benefits cs mode, no-busy indicator single or multiple adcs connected to spi- compatible digital host. ideally suited for maximum throughput. cs mode, with busy indicator single adc connected to spi-compatible digital host with interrupt input. ideally suited for maximum throughput. daisy-chain mode, no-busy indicator multiple adcs connected to a spi- compatible digital host. ideally suited for multichannel simultaneous sampled isolated applications. daisy-chain mode, with busy indicator multiple adcs connected to a spi- compatible digital host with interrupt input. ideally suited for multichannel simultaneous sampled isolated applications. clk da ta in digita l host conver t config dout sclk cnvst din max1 11 56 MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 18 figure 7. cs no busy indicator mode timing figure 8. cs with busy indicator mode connection diagram cs with busy indicator mode the cs with busy indicator mode is shown in figure 8 where a single adc is connected to a spi-compatible digital host with interrupt input. the corresponding timing is given in figure 9 . a rising edge on cnvst completes the acquisition, initi - ates the conversion and forces dout to high impedance. the conversion continues to completion irrespective of the state of cnvst allowing cnvst to be used as a select line for other devices on the board. t conv t acq din acquisition sclk dout conversion acquisition 12 31 61 71 8 t ddo t en t sclkh t sclkl t hsckcn f t ssckcnf d17 d16 d15 d1 d0 cnvst t cnvpw t cyc t sclk t dis clk da ta in irq ovdd 10k digita l host conver t config dout sclk cnvst din max1 11 56 MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 19 figure 9. cs with busy indicator mode timing when the conversion is complete, dout transitions from high impedance to a low logic level, signaling to the digital host through the interrupt input that data readback can commence. the MAX11156 then enters the acquisition phase. the data bits are then clocked out, msb first, by subsequent sclk falling edges. dout returns to high impedance after the 19th sclk falling edge or when cnvst goes high, and is then pulled to ovdd through the external pullup resistor. t cnvpw d16 d17 busy bit dout sclk acquisition acquisition conversion din cnvst d15 d1 d0 12 34 17 18 19 t conv t acq t cyc t sclkl t sclk t ddo t sclkh t dis t hsckcnf t ssckcnf MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 20 multichannel cs confguration, asynchronous or simultaneous sampling the multichannel cs configuration is generally used when multiple MAX11156 adcs are connected to an spi- compatible digital host. figure 10 shows the connection diagram example using two MAX11156 devices. figure 11 shows the corresponding timing. asynchronous or simultaneous sampling is possible by controlling the cs1 and cs2 edges. in figure 10 , the dout bus is shared with the digital host limiting the throughput rate. however, maximum throughput is pos - sible if the host accommodates each adcs dout pin independently. a rising edge on cnvst completes the acquisition, initiates the conversion and forces dout to high impedance. the conversion continues to completion irrespective of the state of cnvst allowing cnvst to be used as a select line for other devices on the board. however, cnvst must be returned high before the minimum conversion time for proper operation so that another conversion is not initiated with insufficient acquisition time and data correctly read out of the device. when the conversion is complete, the MAX11156 enters the acquisition phase. each adc result can be read by bringing its cnvst input low, which consequently outputs the msb onto dout. the remaining data bits are then clocked by subsequent sclk falling edges. for each device, its dout will return to a high-impedance state after the 18 th sclk falling edge or when cnvst goes high. this control allows multiple devices to share the same dout bus. figure 10. multichannel cs configuration diagram max1 1 156 max1 1 156 clk da ta in digita l host cs2 cs1 config dout sclk device b cnvst sclk device a cnvst din dout din MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 21 figure 11. multichannel cs configuration timing daisy-chain, no-busy indicator mode the daisy-chain mode with no-busy indicator is ideally suited for multichannel isolated applications that require minimal wiring complexity. simultaneous sampling of multiple adc channels is realized on the serial inter - face where data readback is analogous to clocking a shift register. figure 12 shows a connection diagram of two MAX11156s configured in a daisy chain. the corre - sponding timing is given in figure 13 . a rising edge on cnvst completes the acquisition and initiates the conversion. once a conversion is initiated, it continues to completion irrespective of the state of cnvst. when a conversion is complete, the msb is presented onto dout and the MAX11156 returns to the acquisition phase. the remaining data bits are stored within an internal shift register. to read these bits out, cnvst is brought low and each bit is shifted out on sub - sequent sclk falling edge. the din input of each adc in the chain is used to transfer conversion data from the previous adc into the internal shift register of the next adc, thus allowing for data to be clocked through the multichip chain on each sclk falling edge. each adc in the chain outputs its msb data first requiring 18 n clocks to read back n adcs. in daisy-chain mode, the maximum conversion rate is reduced due to the increased readback time. for instance, with a 5ns digital host setup time and 3v inter - face, up to four MAX11156 devices running at a conver - sion rate of 279ksps can be daisy-chained. daisy-chain with busy indicator mode the daisy-chain mode with busy indicator is ideally suited for multichannel isolated applications that require minimal wiring complexity while providing a conversion complete indication that can be used to interrupt a host processor to read data. simultaneous sampling of multiple adc channels is real - ized on the serial interface where data readback is analo - gous to clocking a shift register. the daisy-chain mode with busy indicator is shown in figure 14 where three MAX11156s are connected to a spi-compatible digital host with corresponding timing given in figure 15 . a rising edge on cnvst completes the acquisition and initiates the conversion. once a conversion is initiated, it continues to completion irrespective of the state of cnvst. when a conversion is complete, the busy indica tor is pre - sented onto each dout and the MAX11156 returns to the acquisition phase. the busy indicator for the last adc in cnvsta(cs1) cnvstb(cs2) 12 31 71 8 t conv conversion acquisition t cyc d17 d16 d15 d1 d0 t sclkl t sclkh t en t dis t ddo t sclk dout acquisition sclk d17 d16 d1 d0 36 19 20 35 t en d15 21 t dis t cnvpw t cnvpw din t acq t hsckcnf t ssckcnf MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 22 figure 13. daisy-chain, no-busy indicator mode timing figure 12. daisy-chain, no-busy indicator mode connection diagram the chain can be connected to an interrupt input on the digital host. the digital host should insert a 50ns delay from the receipt of this interrupt before reading out data from all adcs to ensure that all devices in the chain have completed conversion. the conversion data is stored within an internal shift reg - ister. to read these bits out, cnvst is brought low and each bit is shifted out on subsequent sclk falling edge. the din input of each adc in the chain is used to transfer conversion data from the previous adc into the internal shift register of the next adc, thus allowing for data to be clocked through the multichip chain on each sclk falling edge. the total of number of falling sclks needed to read back all data from n adcs is 18 n + 1 edges, the one additional sclk falling edge required to clock out the busy mode bit from the host side adc. in daisy-chain mode, the maximum conversion rate is reduced due to the increased readback time. for instance, with a 5ns digital host setup time and 3v interface, up to four MAX11156 devices running at a conversion rate of 276ksps can be daisy-chained on a 3-wire port. max1 1 156 max1 1 156 clk da ta in digita l host config conver t sclk device b cnvst sclk device a cnvst dout d b din din dout d a sclk 12 31 71 8 cnvst t conv conversion acquisition acquisition t acq t sclk t sclkl t sclkh t ddo 34 35 36 19 20 dout b d b 17 d b 16 d b 15 d b 1d b 0d a 17 d a 16 d a 1d a 0 t cnvpw din t cyc 16 t hsckcnf t ssckcn f MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 23 figure 15. daisy-chain mode with busy indicator timing figure 14. daisy-chain mode with busy indicator connection diagram max1 11 56 max1 1 156 clk da ta in irq digita l host config conver t sclk device c cnvst sclk device b cnvst dout d c din din dout d b max1 1 156 sclk device a cnvst din dout d a t conv acquisition conversion dout a = din b dout b = din c dout c cnvst din sclk acquisition t cnvpw t acq t sclk t sclkh 12 34 17 18 19 20 21 33 34 35 36 37 53 54 55 t sclkl t ddo t cyc busy bi t busy bi t busy bi t d a 17 d b 17 d c 17 d c 16 d c 15 d a 16 d a 15 d b 16 d b 15 d a 1 d b 1 d c 1 d a 0 d b 0 d c 0 d a 17 d b 17 d a 18 d b 16 d a 1 d a 17 d a 16 d a 1d a 0 d a 0 d b 1d b 0 t hsckcnf t ssckcnf MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 24 layout, grounding, and bypassing for best performance, use pcbs with ground planes. ensure that digital and analog signal lines are separated from each other. do not run analog and digital lines paral - lel to one another (especially clock lines), and avoid run - ning digital lines underneath the adc package. a single solid gnd plane configuration with digital signals routed from one direction and analog signals from the other provides the best performance. connect the gnd and agnds pins on the MAX11156 to this ground plane. keep the ground return to the power-supply low impedance and as short as possible for noise-free operation. a 500pf c0g (or npo) ceramic chip capacitor should be placed between ain+ and the ground plane as close as possible to the MAX11156. this capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit. for best performance, connect the ref output to the ground plane with a 16v, 10 f f ceramic chip capacitor with a x5r or x7r dielectric in a 1210 or smaller case size. ensure that all bypass capacitors are connected directly into the ground plane with an independent via. bypass v dd and ovdd to the ground plane with 0.1 f f ceramic chip capacitors on each pin as close as pos - sible to the device to minimize parasitic inductance. add at least one bulk 10 f f decoupling capacitor to v dd and ovdd per pcb. for best performance, bring a v dd power plane in on the analog interface side of the MAX11156 and a ovdd power plane from the digital interface side of the device. defnitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. for these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. for these devices, the dnl of each digital output code is measured and the worst-case value is reported in the electrical characteristics table. a dnl error specification of less than q 1 lsb guarantees no missing codes and a monotonic transfer function. offset error for the MAX11156, the offset error is defined at the cen - ter of code 0x2000. the center of code 0x2000 should occur with an analog input voltage of exactly 0v. the offset error is defined as the deviation between the actual analog input voltage required to produce the center of code 0x2000 and the ideal analog input of 0v, expressed in lsbs. gain error gain error is defined as the difference between the change in analog input voltage required to produce a top code transition minus a bottom code transition, subtracted from the ideal change in analog input voltage on (5.0v/4.096v) x v ref x (262142/262144). for the MAX11156, top code transition is 0x3fffe to 0x3ffff. the bottom code tran - sition is 0x00000 and 0x00001. for the MAX11156, the analog input voltage to produce these code transitions is measured and then the gain error is computed by subtract - ing 2.0 x (5.0v/4.096v) x v ref x (262142/262144) from this measurement. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of the full- scale analog input power to the rms quantization error (residual error). the ideal, theoretical minimum analog- to-digital noise is caused by quantization noise error only and results directly from the adcs resolution (n bits): snr = (6.02 x n + 1.76)db in reality, there are other noise sources besides quantiza - tion noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the power signal to the power noise, which includes all spectral components not including the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequencys power to the power of all the other adc output signals: u signal sinad(db) 10 log (noise distortion) MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 25 effective number of bits the effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adcs error consists of quantiza - tion noise only. with an input range equal to the full-scale range of the adc, calculate the enob as follows: sinad 1.76 enob 6.02 ? = total harmonic distortion total harmonic distortion (thd) is the ratio of the power contained in the first five harmonics of the converted data to the power of the fundamental. this is expressed as: ( ) +++ = 22 2 2 23 4 5 2 1 pp p p thd 10 log p where p 1 is the fundamental power and p 2 through p 5 is the power of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the power of the fundamental (maximum signal component) to the power of the next-largest frequency component. aperture delay aperture delay (t ad ) is the time delay from the sampling clock edge to the instant when an actual sample is taken. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in aperture delay. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc in a manner that ensures that the signals slew rate does not limit the adcs performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3db. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. this point is defined as full-power input bandwidth frequency. MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
maxim integrated 26 selector guide package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ordering information +denotes a lead(pb)-free/rohs-compliant package. *ep = exposed pad. package type package code outline no. land pattern no. 12 tdfn-ep td1233+1 21-0664 90-0397 part bits input range (v) reference package speed (ksps) max11150 18 0 to 5 internal max-10 500 max11152 18 0 to 5 external max-10 500 max11154 18 0 to 5 internal/external 3mm x 3mm tdfn-12 500 MAX11156 18 5 internal/external 3mm x 3mm tdfn-12 500 max11158 18 5 internal max-10 500 part temp range pin-package MAX11156etc+t -40c to +85c 12 tdfn-ep* MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn www.maximintegrated.com
? 2013 maxim integrated products, inc. 27 revision history revision number revision date description pages changed 0 3/13 initial release maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX11156 18-bit, 500ksps, 5v sar adc with internal reference in tdfn for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.

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